Realization of radar data acquisition and image large screen display based on SOPC technology
Radar data acquisition and image display are a basic application of radar, and are widely used in military, meteorological forecasting, environmental monitoring, ship navigation and other fields. Radar data is characterized by real-time and high speed. In general, the clock frequency for sampling radar signals is above 100 MHz, and the data throughput of radar data acquisition and processing units is required to be above Gbits/s. Therefore, to achieve a radar data acquisition and image display system, the processing speed of the processor is very high. The traditional radar data acquisition and image display system uses a microprocessor + FPGA (or DSP) solution, using the microprocessor to implement the operating system, radar GUI and display control, using FPGA (or DSP) to achieve high-speed radar data acquisition and processing The disadvantage of this scheme is that it is difficult to achieve large-screen display of radar images with resolutions above 800*600, either with higher processor speed or with independent graphics support, which increases system complexity and cost. .
SOPC is a special system-on-chip based on programmable logic technology. It implements a large and complete electronic system on an FPGA chip as much as possible. It has hardware that can be tailored, scalable, and scalable. The system programmable features make the designed system have great advantages in terms of scale, function, volume, performance, time to market, and development cost. The core frequency of the soft-core processor based on SOPC technology is not very high. At present, the highest frequency of Xilinx's microblaze processor is 210MHz and 240DMIPS. The highest frequency of Altera's NIOS II processor is 340MHz and 290DMIPS. However, due to its extreme flexibility, it can be designed by software and hardware to solve the problem that requires a high-speed processor to achieve the problem when the processor speed is not high.
Based on SOPC technology, this paper proposes a method to realize radar data acquisition and image large screen display on soft core processor with lower frequency.
2 overall design
This design uses the microblaze soft core processor as the development platform, and the SOPC system block diagram is shown in Figure 1.
Figure 1 system hardware block diagram
This design solves the problem of radar data acquisition, processing and large-screen image display on SOPC soft core processor with lower frequency by the following methods.
First, radar data acquisition, processing, and display controllers are implemented using FPGA hardware logic design. The radar data acquisition and processing module is responsible for the control of the radar unit, the ADC chip and the processing of the radar data. The display controller module completes the management of the display data and the driving of the display.
Second, use DMA transfer. The DMA is responsible for collecting and processing the radar data and sending it to the memory through the DMA channel.
Finally, according to the configurable and tailorable features of SOPC hardware, the radar data acquisition and processing module, display control module and DMA module are mounted as devices of the microblaze processor to the peripheral local bus [4].
Since the internal logic of the radar number acquisition, processing module and display control module is completed by the FPGA hardware logic, the microprocessor does not need to directly control the radar unit and the ADC, and does not need to perform complex radar data processing, and does not need to perform the memory data. Management, without controlling the generation of high-speed signal-driven display, thus greatly reducing the burden on the processor, coupled with the use of DMA transmission, the processor only needs to handle the DMA transmission request and the transmission completion interrupt, so that the processor transfers from heavy data. I was freed from it. Through the above approach, the burden on the processor has become very light, so that lower processor speed can handle the task of the system. Moreover, the display control is implemented by the FPGA hardware. The other advantage is that the resolution of the display has little influence on the burden of the processor, so that the image display of the large screen can also be supported in the case of a low processor.
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