Design of video application OSD based on FPGA
In recent years, digital video surveillance systems have been widely used in various fields such as banks, highways, and buildings. In the digital video surveillance system, OSD (On Screen Display) technology is an indispensable part. OSD provides users with a friendly man-machine interface, enabling users to obtain more additional information.
System Composition The system introduced in this article is a complete video monitoring system based on TI DSP TMS320DM6? 3 and FPGA, which supports 1 video input and 1 video output, and also provides a network interface.
The video input is realized by TI's cost-effective video decoder TVP5150A. TVP5150A can realize the collection of two composite video inputs or one S-video video signal. Register configuration through I2C, output digital video signal follows ITU656 standard.
The TVP5150A decoded digital video signal is transmitted to the DSP through the video port 1 of DM6? 3, and the necessary video processing is performed by the DSP and output to the remote device through the network interface. On the other hand, the DM6? 3 processes the video data received from the network, passes through the video port 2, passes through the FPGA, and is displayed and output by the SAA7105. The specific structure is shown in Figure 1.
The output part is implemented with SAA7105. SAA7105 is a high-performance video encoder from NXP, which can provide composite video output, VGA video output, and HDTV high-definition video signal output. The control of SAA7105 is also realized through I2C, receiving the composite digital video signal of ITU656 standard.
The video processing part uses TI's DSP TMS320DM6? 3 to achieve. DM6? 3 main frequency can reach 600MHz, there are two 20-bit video ports, the video port supports digital video interfaces such as BT.656, Y / C, etc. DM6? 3 also integrates a network MAC to achieve network access.
The development speed of hardware performance is always difficult to meet the needs of software. In the increasingly complex application of video processing, DSP undertakes complicated video processing tasks and resources become very tight, so in this system design, FPGA is used to realize the design of OSD, which can reduce the burden of DSP.
Part of the OSD implementation is XC3S250E from Xilinx. The XC3S250E is a Xilinx SPARTAN-3E series FPGA with 250,000 logic gates.
Figure 1: Schematic diagram of the complete video surveillance system architecture based on TMS320DM6? 3 and FPGA
OSD implementation
SAA7105 can not realize the OSD function, but by XC3S250E. The main control chip DM6? 3 only needs to inform the FPGA of the content and location to be displayed, and the specific work is performed by the FPGA. The logic block diagram of OSD is shown as in Fig. 2.
Figure 2: OSD functional block diagram
The OSD FPGA receives OSD data and control instructions from the DSP DM6? 3 through EMIFA, receives video data through the video port 1 of the DSP, and superimposes the OSD information on the video data to output to the video encoder SAA7105. The functional modules of the OSD are described below.
The data port of the address decoding module interfaces with the EMIFA low 32-bit data of DSP DM6? 3, and receives the data and control information sent by DM6? 3. These data and control information are the original 32-bit data sent by DM6? 3. The address decoding module puts the received OSD data, such as the content of the OSD, into the internal FIFO of the FPGA in a 32-bit data format. The control information mainly controls the OSD through a set of control registers.
The module directly connected with the DSP also has a video interface module. The video interface module is connected to the video port 2 of the DSP and stores data and control information from the DSP video port. The control information is directly transmitted to the OSD multi-channel control module, and the control information also directly controls the video decoder SAA7105.
The OSD control logic outputs the control information obtained from the control register group to the various functional modules of the OSD to realize the control of the OSD. The register set is mainly divided into two parts: one is the asynchronous register set, which sends control information such as reset, OSD enable, and data width selection to the OSD; the other is the synchronous register set, which mainly controls the position information of the OSD.
The OSD decoding module takes out the data to be displayed from the FIFO according to the control information of the control logic, and outputs it to the OSD CLUT module in synchronization with the video data. The data obtained from the FIFO is the original DSP 32-bit data, and the data required by the OSD CLUT module is 8/16 bits, so the OSD unpacking module needs to unpack the 32-bit data according to certain rules, at the frequency of the video port Transfer 32-bit data to OSD CLUT module with 8/16 width.
Another function of the FIFO module is to transfer FIFO status information to the DMA event generator module, such as FIFO full or FIFO empty. The DMA event generator monitors these events, and if it occurs, it is sent to the DM6? 3 in an interrupt mode to achieve correct read and write operations to the FIFO.
The OSD CLUT module looks up the corresponding value of YCbCr for the data of each pixel received from the OSD unpacking module, and controls the output order of these OSD CLUT data. This conversion relationship is transmitted by the DSP through the 24-bit data port. The data of the OSD CLUT module is directly output to the OSD multi-controller module.
The OSD multi-channel control module determines the output video data according to the Alpha control bits received from the OSD CLUT module. If the OSD information is currently available, that is, the Alpha control bits are valid, the OSD data is output to the data conversion module. Otherwise, the original video data received from the video interface module is output to implement the OSD function.
The data output by the OSD multi-channel controller is not directly sent to the video decoder, but through the data conversion module, according to the specific application conditions, the necessary data format conversion. According to the interface timing of SAA7105, when the SAA7105 is configured for composite video output, the data required is a single clock edge data. At this time, the data conversion module does not do any work, and the data received from the OSD multi-control module is transmitted unchanged. To SAA7105; if SAA7105 is configured in VGA or HDTV output mode, dual clock edge data is required, at this time the data conversion module converts the single clock edge data received from the OSD controller into dual clock edge data and outputs it to the video decoder SAA7105 .
This shows that FPGA has completed all the work of OSD. If you want to display the OSD content, DM6? 3 only needs to send control commands to the FPGA through the EMFIA port. These commands certainly include the OSD content and location information.
OSD control
The OSD design implemented by XC3S250E performs OSD display based on the received OSD location and content information, without any restrictions on the content displayed by the OSD, and is very flexible and convenient. The following uses OSD Chinese character display as an example to explain the control operation of OSD.
In order to display Chinese characters correctly, it is necessary to convert the internal code of the input Chinese characters into the corresponding area code. This function we use the function Uint32 Code_Converse (unsigned char * CodeNPointer), whose input is a pointer to the Chinese characters to be converted. The return value is the region code corresponding to the Chinese character. The display of OSD is realized by the function OSDHZ? Isplay:
void OSDHZ_ Display {
Uint8 * pFrame
Uint32 pitch
OSDUTIL_Point * loc
Uint32 CodeQ
OSDHZ? Ont * font
Uint8 fgColor
Uint8 bgColor
}
Among them, Uint8 * pFrame is the buffer buffer for OSD output; Uint32 pitch is the pixel value displayed on each line; OSDUTIL_Point * loc is the display position of the first character; Uint32 CodeQ is the area code of the Chinese character to be displayed; OSDHZ? Ont * font is the font used to display Chinese characters; Uint8 fgColor displays the foreground color of Chinese characters; Uint8 bgColor displays the background color of Chinese characters.
Therefore, if you need to display Chinese characters, you only need to convert the Chinese characters to the necessary code system, and then give the location of the converted area code to the OSD FPGA. Of course, to display Chinese characters, the Chinese character font is essential.
Shareconn development Co.,Ltd assemble high quality RF extension cables, such as BNC cables, SMA cables, MCX cables, Farkra cables, SMB cables and so on.
Accommodates a wide range of medium to miniature sized RG coaxial cables in a rugged . Medium size design.Provides customer flexibility in their design and manufacturing with a durable connector. Available in many styles: Plugs (Straight and Right Angle) and Jacks (Panel Mount , Bulkhead Mount ). Meets many customer application demands.
RF Extension Cable Assembly,RF Extension Coaxial Cable,RF Coaxial Cable,RF Aerial Cable Extension
Shareconn Development CO.,LTD , http://www.share-conn.com